1. Field of Invention
The present invention is related to nonvolatile memories and in particular to the creation of a reference by which the state of Twin MONOS memory cells are evaluated.
2. Description of Related Art
To read data from a nonvolatile memory cell requires that a reference signal be produced to determine whether a signal by a cell being read is a logical “1” or a logical “0”. A common method is to supply the reference signal to a differential sense amplifier to which the reference signal is connected to one input of the sense amplifier. In some cases the sense amplifier compares a bit line voltage to a DC reference voltage. This method can be slow because time is required to allow the bit line to settle. In other schemes a dynamic sensing method is used in which a half current is established to detect the difference between a logical “0” state and a logical “1” state. One challenge is to design a reference circuit, which can produce an output current or voltage that tracks current of a cell being read and can be used to accurately determine the logical state of the cell being read. In addition, the capacitive loading affects of a bit line containing the cell being read needs to be matched by the reference circuit to produce a similar performance between the memory cells and the reference circuit.
In U.S. Pat. No. 6,992,932 (Cohen) a method, circuit and system is directed to determining a reference voltage used to read memory cells that are programmed to a given program state. U.S. Pat. No. 6,954,393 (Lusky et al.) is directed to a method for reading a bit memory cell of a nonvolatile memory cell array. The method comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell where the reference cell comprises a first bit at a first non-ground program state and a second bit at a second non-ground program state. U.S. Pat. No. 6,975,541 (Shappir) is related to reading array cell with matched reference cell where a voltage creates a read disturb and a programmed cell threshold voltage shifts upward allowing reference cell adjustment to keep on-off current ratio constant.
U.S. Pat. No. 6,906,951 (Wong) is directed to an auto-tracking bit line scheme that generates a half cell current by programming reference cells to threshold voltages that are between threshold voltages levels that are used to represent data. U.S. Pat. No. 6,219,279 (Manolescu et al.) is directed to a method and circuits in a nonvolatile memory system for limiting bit line current during program operation that includes biasing a driving transistor to mirror a maximum desired current. In U.S. Pat. No. 6,038,169 (Ogura et al.) a reference circuit is directed to producing a reference current to be used in determining the value of data in a flash memory cell. U.S. Pat. No. 5,771,192 (Kim et al.) is directed a bit line reference circuit for a nonvolatile memory device, which performs a reference data access operation using a single bit line having an upper and lower portion, wherein the upper bit line containing an upper reference cell provides a reference signal while a lower bit line cell string is selected.
U.S. Pat. No. 5,754,475 (Bill et al.) is directed to a reference scheme for a multi-bit flash memory in which multiple reference cells are arranged in rows and columns. The number of rows corresponds to the number of rows in the flash memory and the number of columns depends on the number of bits in the multi-bit memory cells. U.S. Pat. No. 5,652,722 (Whitefield) is directed to a floating gate transistor connected to a bit line and a bit line driver circuit comprising a variable impedance device and an active load powering the bit line from a supply node. U.S. Pat. No. 5,638,326 (Hollmer et al.) is directed to a flash memory read and verify circuit that minimizes by design the effects of process, power and temperature variations. The read and verify circuit uses a bias circuit with a cascode transistor for the reference. U.S. Pat. No. 5,629,892 (Tang) is directed to a flash memory where an array of reference cells is separate from the array of memory cells. The transconductance of the reference cells is matched to the transconductance of the memory cells to produce a reference current.
U.S. Pat. No. 5,596,527 (Tomioka et al.) is directed to a multi-bit flash memory with multiple reference cells providing a multiple of threshold voltages. The reference cells are made from memory cells, and the multiple reference cells associated with a word line of memory cells are accessed using the same word line as used for the memory cells. U.S. Pat. No. 5,544,116 (Chao et al.) is directed to a program and erase verify circuit in which different voltages are supplied to the memory and reference cells to read the program and erase verify conditions. U.S. Pat. No. 5,398,203 (Prickett, Jr.) discloses a nonvolatile memory device coupled to current regulating circuitry whereby the regulating circuitry regulates currents during programming. U.S. Pat. No. 5,172,338 (Mehrotra et al.) is directed to a set of reference cells which closely track the multi-bit flash memory cells are used for read and erase verification. In U.S. Pat. No. 4,785,423 (Skupnjak et al.) an architecture is directed to an EPROM PAL wherein sources of cells are coupled to a bit line through a current limiting transistor.
The stored value of a flash memory cell is usually determined by measuring its current or voltage signal with respect to a mid-way reference. In order to achieve both performance and reliability, it is desirable for the reference cell to be precisely controllable, and to match the memory cell characteristics as much as possible. In the first related U.S. Pat. No. 6,038,169 (assigned to the same assignee as the present invention) is described a reference cell, shown in FIG. 1, in which a memory cell 10 is connected in series with a current source 11. In this scheme, the reference current is primarily determined by the current source transistor 11, and the threshold of the memory cell portion 10 does not need to be precisely controlled. It is only necessary that the resistance of the memory cell 10 be significantly lower than the resistance of the current source. As a result of this configuration, a selected memory cell and an activated reference cell should experience the same turn-on delay and capacitive load. The accuracy of this scheme depends upon the current source transistor behaving similarly to the memory cell over variations in process, temperature and voltage.
If the behavior of the current source transistor does not track with the memory cell over variations of process, temperature and voltage, then a different approach is needed. There are several prior art in which a memory cell by itself is used for referencing. In U.S. Pat. No. 5,386,388 (Atwood et al.) is directed to using memory cells to generate the reference signal. In order to improve operation margin and reliability, different memory cells are used in the different modes of program verify and erase verify, as well as normal read.
Multiple program and erase operations, i.e. cycling, can also have a significant effect on memory cell transistor characteristics. In trap-type flash memory cells, threshold voltages may shift over time, or with increasing numbers of cycles. U.S. Pat. No. 6,992,932 (Cohen) is directed towards a dynamically adjustable reference based on taking a sample of known-cell values. In this scheme, it is expected that the programmed cell thresholds will shift down over time. It is assumed that the degree of threshold shift is the same for all of the memory cells; therefore, it is possible to sample a small number of cells to determine the degree of shift, find the appropriate reference level to correctly read those cells, and then apply that reference level to read the rest of the memory array.
In the second related U.S. Pat. No. 6,399,441 (assigned to the same assignee as the present invention) the Twin MONOS memory cell shown in FIG. 2 is described. The twin MONOS memory cell has two storage sites 26, 27 within a single cell device. A word gate device 20 is sandwiched between two control gate devices 21 and 22. In order to keep the storage regions independent from each other, a control gate override scheme is utilized. For example, when a selected side is read, the control gate of the unselected side is raised to a high voltage (override), and thus the state of the unselected side will have a negligible impact on the signal. However, in the event that the signal current itself is low, i.e. if both sides of the cell are programmed to high threshold states, the signal interference from the unselected side may become more significant.